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white electronic designs corporation ? (502) 366-5151 www.whiteedc.com

the wed2zlrsp01s, dual independent array, nbl-ssram device employs high-speed, low-power cmos silicon and is fabricated using an advanced cmos process. wedc?s 24mb, sync burst sram mcp integrates two totally inde- pendent arrays, the first organized as a 512k x 32, and the second a 256k x 32. all synchronous inputs pass through registers controlled by a positive edge triggered, single clock input per array. the nbl or no bus latency memory provides 100% bus utilizaton, with no loss of cycles caused by change in modal operation (write to read/read to write). all inputs except for asynchronous output enable and burst mode control are synchronized on the positive or rising edge of clock. burst order control must be tied either high or low, write cycles are internally self-timed, and writes are initiated on the rising edge of clock. this feature eliminates the need for complex off-chip write pulse generation and proved increased timing flexibility for incoming signals.

fast clock speed: 166, 150, 133, and 100mhz fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns fast oe access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns single +2.5v 5% power supply (vdd) snooze mode for reduced-standby power individual byte write control clock-controlled and registered addresses, data i/os and control signals burst control (interleaved or linear burst) packaging: 209-bump bga package low capacitive bus loading april 2002 rev. 0 eco #15203 1 2 3 4 5 6 7 8 9 10 11 av ss a_dat b 0 a_dat b 1 a_dat b 2 a_dat b 3 v ss a_dat a 0 a_dat a 1 a_dat a 2 a_dat a 3 v ss b nc a_dat b 4 a_dat b 5 a_dat b 6 a_dat b 7 v ss a_dat a 4 a_dat a 5 a_dat a 6 a_dat a 7 nc c a_adr a_adr a_oe a_adv a_bwe b v ss a_bwe a a_zz a_adr a_adr a_adr d a_adr v ss a_cke v cc v cc v cc v cc v cc v cc a_adr a_adr e a_adr a_clk a_gwe v cc v cc v cc v cc v cc v cc a_adr 1 a_adr 0 f a_adr v ss a_cs 2 v cc v cc v cc v cc v cc v cc a_adr a_adr g a_adr a_adr a_cs 1 a_cs 2 a_bwe c v ss a_bwe d a_lbo a_adr a_adr a_adr h nc a_dat c 0 a_dat c 1 a_dat c 2 a_dat c 3 v ss a_dat d 0 a_dat d 1 a_dat d 2 a_dat d 3 nc jv ss a_dat c 4 a_dat c 5 a_dat c 6 a_dat c 7 v ss a_dat d 4 a_dat d 5 a_dat d 6 a_dat d 7 v ss kv ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss lv ss b_dat b 0 b_dat b 1 b_dat b 2 b_dat 3 v ss b_dat a 0 b_dat a 1 b_dat a 2 b_dat a 3 v ss m nc b_dat b 4 b_dat b 5 b_dat b 6 b_dat 7 v ss b_dat a 4 b_dat a 5 b_dat a 6 b_dat a 7 nc n b_adr b_adr b_oe b_adv b_bwe b v ss b_bwe a b_zz b_adr b_adr b_adr p b_adr v ss b_cke v cc v cc v cc v cc v cc v cc b_adr b_adr r b_adr b_clk b_gwe v cc v cc v cc v cc v cc v cc b_adr 1 b_adr 0 t b_adr v ss b_cs 2 v cc v cc v cc v cc v cc v cc b_adr b_adr u b_adr nc b_cs 1 b_cs 2 b_bwe c v ss b_bwe d b_lbo b_adr b_adr b_adr v nc b_dat c 4 b_dat c 5 b_dat c 6 b_dat c 7 v ss b_dat d 4 b_dat d 5 b_dat d 6 b_dat d 7 nc wv ss b_dat c 0 b_dat c 1 b_dat c 2 b_dat c 3 v ss b_dat d 0 b_dat d 1 b_dat d 2 b_dat d 3 v ss
white electronic designs corporation westborough, ma (508) 366-5151

white electronic designs corporation (502) 366-5151 www.whiteedc.com
write operation occurs when we is driven low at the rising edge of the clock. bw[d:a] can be used for byte write operation. the pipe-lined nbl ssram uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycle later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates after 2 cycles of wake up time.

the wwed2zlrsp01s is an nbl dual array ssram designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe, lbo and zz) are synchronized to rising clock edges, and all features are available on each of the independent arrays. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally gen- erated by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable (cke) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device reg- isters will hold their previous values. nbl ssram latches external address and initiates a cycle when cke and adv are driven low at the rising edge of the clock. output enable (oe) can be used to disable the output at any given time. read operation is initiated when at the ris- ing edge of the clock, the address presented to the ad- dress inputs are latched in the address register, cke is driven low, the write enable input signals we are driven high, and adv driven low. the internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. at the second clock edge the data is driven out of the sram. during read operation oe must be driven low for the device to drive out the requested data. note 1: lbo pin must be tied to high or low, and floating state must not be allowed.
! " first address 0 0011011 01001110 10110001 fourth address 1 1100100
#$ ! " % % % % first address 0 0 0 11011 01101100 10110001 fourth address 1 1 0 00110

white electronic designs corporation westborough, ma (508) 366-5151
& '( )& ) & & ** + # hl xxx l n/a deselect xh xxx l n/a continue deselect ll hxl l external address begin burst read cycle xh xx l l next address continue burst read cycle ll hxh l external address nop/dummy read xh xxh l next address dummy read ll llx l external address begin burst write cycle xh x l x l next address continue burst write cycle ll lhx l n/a nop/write abort xh xhx l next address write abort xx xxx h current address ignore clock ,- -./ .0 & 0& .0 & )& ) )1 )* ) + # hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllll write all bytes l hhhh write abort/nop notes: 1. x means ?don?t care.? 2. all inputs in this table must meet setup and hold time around the rising edge of clk ( ). 3. applies to each of the independent arrays. notes: 1. x means ?don?t care.? 2. the rising edge of clock is symbolized by ( ) 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins (zz and oe). 6. cex refers to the combination of ce 1 , ce 2 and ce 2 . 7. applies to each of the independent arrays.
white electronic designs corporation (502) 366-5151 www.whiteedc.com
/.0& 2 . 0-/ voltage on v dd supply relative to v ss -0.3v to +3.6v v in (dqx) -0.3v to +3.6v v in (inputs) -0.3v to +3.6v storage temperature (bga) -55c to +125c short circuit output current 100ma &0 0&/0/
*stress greater than those listed under ?absolute maximum ratings?: may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability. ' *+# /341# ## 5 . -# input high (logic 1) voltage v ih 1.7 v dd +0.3 v 1 input low (logic 0) voltage v il -0.3 0.7 v 1 input leakage current i li 0v v in v dd -5 5 a 2 output leakage current i lo output(s) disabled, 0v v in v dd -5 5 a output high voltage v oh i oh = -1.0ma 2.0 --- v 1 output low voltage v ol i ol = 1.0ma --- 0.4 v 1 supply voltage v dd 2.375 2.625 v 1 notes: 1. all voltages referenced to v ss (gnd) 2. zz pin has an internal pull-up, and input leakage is higher. 0&/0/ notes: 1.i dd is specified with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. 2. typical values are measured at 2.5v, 25c, and 10ns cycle time. "0-& notes: 1. this parameter is sampled. ' *+# /341# ## 03+ 5 . -# control input capacitance c i t a = 25c; f = 1mhz 5 7 pf 1 input/output capacitance (dq) c o t a = 25c; f = 1mhz 6 8 pf 1 address capacitance c a t a = 25c; f = 1mhz 5 7 pf 1 clock capacitance c ck t a = 25c; f = 1mhz 3 5 pf 1 66 7% %% ' *+# /341# ## 03+ 8 8 8 8 . -# power supply i dd device selected; all inputs v il or v ih ; cycle 650 600 560 500 ma 1, 2 current: operating time = t cyc min; v dd = max; output open power supply i sb 2 device deselected; v dd = max; all inputs v ss + 0.2 30 60 60 60 60 ma 2 current: standby or v dd - 0.2; all inputs static; clk frequency = 0; zz v il power supply i sb 3 device selected; all inputs v il or v ih ; cycle 20 40 40 40 40 ma 2 current: current time =t cyc min; v dd = max; output open; zz v dd - 0.2v clock running i sb 4 device deselected; v dd = max; all inputs 140 120 100 80 ma 2 standby current v ss + 0.2 or v dd - 0.2; cycle time = t cyc min; zz v il
white electronic designs corporation westborough, ma (508) 366-5151
0&/0/ 1. all address inputs must meet the specified setup and hold times for all rising clock (clk) edgeswhen adv is sampled low and c ex is sampled valid. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low. a read cycle is defined by we high with adv low. both cases must meet setup and hold times. 4. applies to each of the independent arrays. .0".0 '
.0".0 '
9 : :& :& -' :
/341# 66 8 7% 8 8 %% 8 "4 5 5 5 5 . clock time t cyc 6.0 6.7 7.5 10.0 ns clock access time t cd ? 3.5 ? 3.8 ? 4.2 ? 5.0 ns output enable to data valid t oe ? 3.5 ? 3.8 ? 4.2 ? 5.0 ns clock high to output low-z t lzc 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns output hold from clock high t oh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns output enable low to output low-z t lzoe 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns output enable high to output high-z t hzoe ? 3.0 ? 3.0 ? 3.5 ? 3.5 ns clock high to output high-z t hzc ? 3.0 ? 3.0 ? 3.5 ? 3.5 ns clock high pulse width t ch 2.2 ? 2.5 ? 3.0 ? 3.0 ? ns clock low pulse width t cl 2.2 ? 2.5 ? 3.0 ? 3.0 ? ns address setup to clock high t as 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns cke setup to clock high t ces 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns data setup to clock high t ds 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns write setup to clock high t ws 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns address advance to clock high t advs 1.5 1.5 1.5 1.5 ns chip select setup to clock high t css 1.5 1.5 1.5 1.5 ns address hold to clock high t ah 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns cke hold to clock high t ceh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns data hold to clock high t dh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns write hold to clock high t wh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns address advance to clock high t advh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns chip select hold to clock high t csh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns *including scope and jig capacitance &/0 -'0-/ '' -&// 0&)/& "&9&'
"4 ( input pulse level 0 to 2.5v input rise and fall time (measured at 20% to 80%) 1.0v/ns input and output timing reference levels 1.25v output load see output load (a)
white electronic designs corporation (502) 366-5151 www.whiteedc.com

snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time z is in a high state. after the device enters snooze mode, all inputs except zz become gated in- puts and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb 2 z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. -:& '& ' *+# ## /341# 5 . -# current during snooze mode zz v ih i sb 2 z 10 ma zz active to input ignored t zz 2(t kc )ns 1 zz inactive to input sampled t rzz 2(t kc )ns1 zz active to snooze current t zzi 2(t kc )ns 1 zz inactive to exit snooze current t rzzi ns 1 snooze mode timing diagram
white electronic designs corporation westborough, ma (508) 366-5151
timing waveform of read cycle note: applies to both independent arrays.
white electronic designs corporation (502) 366-5151 www.whiteedc.com
timing waveform of write cycle note: applies to both independent arrays.

white electronic designs corporation westborough, ma (508) 366-5151
timing waveform of single read/write note: applies to both independent arrays.
white electronic designs corporation (502) 366-5151 www.whiteedc.com
timing waveform of cke operation note: applies to both independent arrays.
white electronic designs corporation westborough, ma (508) 366-5151
timing waveform of ce operation note: applies to both independent arrays.
white electronic designs corporation (502) 366-5151 www.whiteedc.com
& & " -& 0
"-41 #;# #*< + 0 4+

8 wed2zlrsp01s35bc 512k x 32/256k x 32 3.5 166 commercial 0 - 70 c wed2zlrsp01s38bc 512k x 32/256k x 32 3.8 150 commercial 0 - 70c wed2zlrsp01s42bc 512k x 32/256k x 32 4.2 133 commercial 0 - 70c wed2zlrsp01s50bc 512k x 32/256k x 32 5.0 100 commercial 0 - 70c wed2zlrsp01s38bi 512k x 32/256k x 32 3.8 150 industrial -40 - 85c wed2zlrsp01s42bi 512k x 32/256k x 32 4.2 133 industrial -40 - 85c wed2zlrsp01s50bi 512k x 32/256k x 32 5.0 100 industrial -40 - 85c

119 bump pbga all linear dimensions are in millimeters and parenthetically in inches

ball attach pad for above bga package is 620 microns in diameter. pad is solder mask defined.

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